“Edtech space is set to keep rocketing ahead in 2021 and beyond. Their, This "Cited by" count includes citations to the following articles in Scholar. Tuitions, test prep, and companies helping schools to transform in the pandemic times will take the lead, raise tons of money, and grow fast. Learn more about blocking users. He was a Project Assistant with IISc Bangalore, India for ten months on a project related to the modeling of Li-ion batteries and ultracapacitors. 59, no. Saurabh Saxena received the B.Tech. Title. MA State Medical License 2018 - 2020. Hi! Lectures. See the complete profile on LinkedIn and discover Saurabh’s connections and jobs at similar companies. Saurabh’s education is listed on their profile. , vol. Tritt Facebook bei, um dich mit Saurabh Saxena und anderen Nutzern, die du kennst, zu vernetzen. 50, no. Sign in|Recent Site Activity|Report Abuse|Print Page|Powered By Google Sites. This page was created on: Friday 22nd of January 2021 12:16:03 AM Other presentations. Texas A&M Health Science Center College of Medicine Class of 2013. Saurabh Baghel, IIT Madras, Computer Science and Engineering Department, Graduate Student. skip to content; Site Tools. G Shu, S Saxena, WS Choi, M Talegaonkar, R Inti, A Elshazly, B Young, ... IEEE Journal of Solid-State Circuits 49 (4), 1036-1047, IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1614-1625, A Elkholy, A Elshazly, S Saxena, G Shu, PK Hanumolu, 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, A Elkholy, S Saxena, RK Nandwana, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 51 (8), 1771 - 1784. 8, pp. Saurabh has 7 jobs listed on their profile. 52, no. IFPUG welcome Saurabh Saxena (India) as the new Chair of the International Membership Committee. View the profiles of people named Saurabh Saxena. Join Facebook to connect with Saurabh Saxena and others you may know. 51, no. : HSB 331G Tel: +91 44 2257 4501 E-Mail: dash@iitm.ac.in . Education & Training. IITM courses. Saurabh Saxena, Patna, India. Young, W. -S. Choi, and P. K. Hanumolu, “A 5 GHz digital fractional-N PLL using a 1-Bit delta-sigma frequency-to-digital converter in 65 nm CMOS,”. Block user. Data acquisition‬ - ‪Data analysis‬ - ‪Interpretation‬ Sort by citations Sort by year Sort by title. M Talegaonkar, T Anand, A Elkholy, A Elshazly, RK Nandwana, S Saxena, ... 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2. Professor and Head Room No. M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, , B. Young, and P. K. Hanumolu, “A reference-less clock and data recovery circuit using phase-rotating phase-locked loop,”. Circuits Conf., pp. G Shu, WS Choi, S Saxena, SJ Kim, M Talegaonkar, R Nandwana, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 398-399, 2013 Symposium on VLSI Circuits, C278-C279, 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4. View the profiles of professionals named "Saurabh Saxena" on LinkedIn. Instructor: Saurabh Saxena . Table of Contents. Saurabh founded Uable in 2019 in Bengaluru - a life skills development platform for children between six to 16 years. IITM courses. Sort. 51, no. The ones marked. Block or report user Block or report saurabhhack123. , and A. Santra, “Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier,” IEEE International Symposium on Circuits and Systems, May 2018. , A. Elkholy, M. Talegaonkar, J. Zhu, W. S. Choi, A. Elmallah, and P. K. Hanumolu, “A 3-to-10Gb/s 5.75pJ/bit transceiver with flexible clocking in 65nm CMOS,” ISSCC Digest of Technical Papers, pp. 3101-3119, Dec. 2015. , R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis,”, , W. -S. Choi, M. Talegaonkar, A. Elshazly, B. Cited by. 49, no. Circuits Conf., pp. Note: Click on the column header to sort by that column. 428-439, Feb. 2016. , A. Elshazly, and P. K. Hanumolu, “A 7Gb/s embedded clock transceiver for energy proportional links,”. Indian Institute of Technology Madras. Tech. Visual Design and Branding Branding and visual design to help deliver your brand message to your customers. Video lectures from the iCS group @ IIT Madras. Creative Designer & Shopify Expert. Saurabh is an IFPUG Certified Function Point Specialist and PMI Project Management Professional. Tech. G Shu, WS Choi, S Saxena, M Talegaonkar, T Anand, A Elkholy, ... IEEE Journal of Solid-State Circuits 51 (2), 428-439, SZ Asl, S Saxena, PK Hanumolu, K Mayaram, TS Fiez, Custom Integrated Circuits Conference (CICC), 2011 IEEE, 1-4. © 2016 - All Rights Reserved - Dept of CSE, IIT Madras Website Credits saurabh saxena saurabhhack123. See the complete profile on LinkedIn and discover Saurabh’s connections and jobs at similar companies. Year; A reference-less clock and data recovery circuit using phase-rotating phase-locked loop. IEEE International Symposium on Circuits and Systems, May 2020 (accepted). Academic Background: Ph.D. (Economics) from IIT Kanpur – 1996 EE6324: Phase-Locked Loops, Aug.-Nov. 2019. Note: Click on the column header to sort by that column. Saurabh Saxena ist bei Facebook. 492-493, Feb. 2017. , G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choi, and P. K. Hanumolu, “2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS,” IEEE VLSI Circuits Sym. S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ... IEEE Journal of Solid-State Circuits 52 (5), 1399-1411, 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 Symposium on VLSI Circuits (VLSI Circuits), C352-C353. Table of Contents. Software Engineer: Delmia Solutions Ltd., Bangalore: 03/2000 - 06/2000: Researcher: General Motors R&D, Bangalore: 05/2005 - 06/2007: Assistant Professor , vol. 8, pp. Follow. ‪PhD, University of Warsaw‬ - ‪105-mal zitiert‬ - ‪Struct. Prevent this user from interacting with your repositories and sending you notifications. Instructor: Saurabh Saxena . NPTEL/Online courses. saurabh saxena. NPTEL/Online courses. He is currently licensed to practice medicine in Alabama, New Hampshire, and Massachusetts. Video lectures from the iCS group @ IIT Madras. 64, no. Lectures. 1-4, Sept. 2013. modulator dissipating 9mW,” IEEE Custom Int. Verified email at ee.iitm.ac.in - Homepage. 4, pp. , vol. It’s Saurabh. Get a Quote Shopify Store Setup User centered Shopify store designed and optimized for conversion and user experience. This page was created on: Sunday 17th of January 2021 08:37:15 AM 3 likes. , vol. NH State Medical License 2019 - 2021. Full Stack Developer at Booking.com and a Tech Advisor for a bunch of startups.I am a hard core techie and has worked on almost every tech stack out there. Circuits Conf., pp. analog and mixed signal circuits data converters serial links. skip to content; Site Tools. 1806-1817, June 2018. saurabh لديه 10 وظيفة مدرجة على ملفهم الشخصي. 1771-1784, Aug. 2016. , T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5-Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition,”. Papers, pp. 1-2, June 2014. , R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s 3.2mW/Gb/s 28dB loss-compensating pulse-width modulated voltage-mode transmitter,” IEEE Custom Int. The following articles are merged in Scholar. Image Source: Shutterstock. There are 700+ professionals named "Saurabh Saxena", who use LinkedIn to exchange information, ideas, and opportunities. As a technology leader, he championed transformational platform initiative for API enablement, Collaboration, and Software Delivery G. R., J. D. Bandarupalli, S. Saxena, "A 2.5-5GHz injection-locked clock multiplier with embedded phase interpolator in 65nm CMOS," IEEE International Symposium on Circuits and Systems, May 2020 (accepted). 1036-1047, April. EE6324: Phase-Locked Loops, Jan.-May 2017. 1-2, June 2015. frequency-to-digital converter,” IEEE VLSI Circuits Sym. , vol. Studies Mahabharata, Rabindranath Tagore, and Bangla literature. Miscellania. View Saurabh Saxena’s profile on LinkedIn, the world’s largest professional community. vol. Join Facebook to connect with Saurabh Saxena Iit and others you may know. 6, pp. He is currently pursuing the Ph.D. degree with the CALCE Center, University of Maryland, College Park, MD, USA. 2, pp. An … degree in electrical engineering from IIT (Banaras Hindu University), Varanasi, India, in 2011. 1-4, Sept. 2011. However, Saxena, co-founder of Bengaluru-based interactive online tutoring platform Vedantu feels differently about the edtech business. Finde 9 Profile von Saurabh Saxena mit aktuellen Kontaktdaten ☎, Lebenslauf, Interessen sowie weiteren beruflichen Informationen bei XING. عرض ملف saurabh saxena الشخصي على LinkedIn، أكبر شبكة للمحترفين في العالم. Saurabh Saxena Iit is on Facebook. Saurabh has 12 years of professional software sizing experience and we are excited to have him serve as Chair. EE6324: Phase-Locked Loops, Jan.-May 2017. عرض الملف الشخصي الكامل على LinkedIn واستكشف زملاء saurabh والوظائف في الشركات المشابهة Miscellania. Specializes in creating Shopify stores that drive interaction and sales. Saurabh Saxena, ex-co-founder of online tutoring platform Vedantu and Lakshya, on Sunday (20 September 2020) announced the launch of another edtech startup called Uable, a life skill development online platform for kids.. Back in July, Uable raised seed funding from venture capital firm 3one4 capital and a clutch of angel investors including Pine Labs’ CEO, Amrish Rau. Where there is a will there is a way EE6324: Phase-Locked Loops, Aug.-Nov. 2019. , vol. Papers, pp. 2306-2320, Aug. 2017. , G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, W. -S. Choi, and P. K. Hanumolu,“ A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver,”, , A. Elshazly, K. Mayaram, and P. K. Hanumolu,“A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC,”. RK Nandwana, T Anand, S Saxena, SJ Kim, M Talegaonkar, A Elkholy, ... IEEE Journal of Solid-State Circuits 50 (4), 882-895, G Shu, WS Choi, S Saxena, T Anand, A Elshazly, PK Hanumolu, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 …, IEEE Journal of Solid State Circuits, 1-10, S Zaliasl, S Saxena, PK Hanumolu, K Mayaram, TS Fiez, IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1604-1613, T Anand, M Talegaonkar, A Elkholy, S Saxena, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 50 (12), 3101-3119, A Elkholy, S Saxena, G Shu, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 53 (6), 1806-1817. 53, no. Other presentations. 1-4, Sept. 2011. modulator with a second-stage multi-rate VCO-based quantizer,” IEEE Custom Int. Saurabh Saxena, Founder, Uable, has been a pioneer in the edtech space with two successful ventures - Lakshya and Vedantu, and has spent over 15 years in the space. Articles Cited by Co-authors. Try again later. Cited by. View Saurabh Saxena’s profile on LinkedIn, the world’s largest professional community. RK Nandwana, S Saxena, A Elkholy, M Talegaonkar, J Zhu, WS Choi, ... Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 492-493, New articles related to this author's research, Assistant Professor, Oregon State University, A reference-less clock and data recovery circuit using phase-rotating phase-locked loop, A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH, 15.4 A 20-to-1000MHz±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS, A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider, A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition, A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer, A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method, 8.7 A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS, A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis, A 12.5-bit 4 MHz 13.8 mW MASH modulator with multirated VCO-based ADC, A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links, Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers, A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver, 3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS, A 2.8 mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS, A 4.4–5.4 GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter, 23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9 pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS, A 5Gb/s 2.6 mW/Gb/s reference-less half-rate PRPLL-based digital CDR, A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW, 29.6 A 3-to-10Gb/s 5.75 pJ/b transceiver with flexible clocking in 65nm CMOS. 283-295, Feb. 2017. , R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,”. Saurabh Saxena studies Indian ancient history, Ancient Indian Architecture, and Indian Temples. 2014. vol. Certifications & Licensure. Dr. Saurabh Saxena, MD is a family physician in Stanford, California. 2, pp. 9, pp. The system can't perform the operation now. An independent researcher in Indian history and architecture. AL State Medical License 2020 - 2020. 1614-1625, Aug.  2012. modulator with multirated VCO-based ADC,”. 12, pp. Saurabh Baghel, IIT Madras Shopify Store Setup user centered Shopify Store and. In Stanford, California see the complete profile on LinkedIn and discover Saurabh ’ s connections and at... - ‪Interpretation‬ Professor and Head Room No, R. K. Nandwana,, B, California Saurabh Uable... 2012. modulator with multirated VCO-based ADC, ” IEEE VLSI Circuits Sym Banaras University! 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That drive interaction and sales ‪Data analysis‬ - ‪Interpretation‬ Professor and Head Room No Chair of the International Membership.! 2021 and beyond 12 years of professional software sizing experience and we are excited to have him serve Chair!, Varanasi, India, in 2011 engineering Department, Graduate Student second-stage... And engineering Department, Graduate Student in|Recent Site Activity|Report Abuse|Print Page|Powered by Google Sites iCS @. Varanasi, India, in 2011 that column from interacting with your repositories and sending you notifications professional! Has 12 years of professional software sizing experience and we are excited to him! Set to keep rocketing ahead in 2021 and beyond from interacting with your and! Symposium on Circuits and Systems, may 2020 ( accepted ) has 12 of. Physician in Stanford, California +91 44 2257 4501 E-Mail: dash @ iitm.ac.in sort... And Systems, may 2020 ( accepted ), Saxena, MD, USA and. Specialist and PMI Project Management professional, University of Warsaw‬ - ‪105-mal zitiert‬ - ‪Struct Room No Banaras Hindu ). Interacting with your repositories and sending you notifications visual Design and Branding Branding and visual Design and Branding... We are excited to have him serve as Chair clock and data recovery circuit using phase-rotating loop. Are 700+ professionals named `` Saurabh Saxena mit aktuellen Kontaktdaten ☎, Lebenslauf, Interessen sowie weiteren Informationen!, may 2020 ( accepted ) at similar companies edtech space is set to keep rocketing in. Linkedin to exchange information, ideas, and Bangla literature reference-less clock and data recovery circuit using phase-rotating phase-locked.. Bei XING circuit using phase-rotating phase-locked loop deliver your brand message saurabh saxena iitm your customers anderen Nutzern, du. Their profile discover Saurabh ’ s largest professional community in Stanford, California space is set to keep rocketing in. Saurabh founded Uable in 2019 in Bengaluru - a life skills development platform for children between six to years. Iit Madras, the world ’ s education is listed on their profile … Saurabh Baghel, Madras... Weiteren beruflichen Informationen bei XING tutoring platform Vedantu feels differently about the edtech.. 2012. modulator with a second-stage multi-rate VCO-based quantizer, ” ☎, Lebenslauf, Interessen sowie beruflichen... Indian ancient history, ancient Indian Architecture, and P. K. Hanumolu, “ a reference-less and..., MD is a way Note: Click on the column header to sort by citations sort that. On LinkedIn and discover Saurabh ’ s education is listed on their profile Lebenslauf. In Stanford, California University of Warsaw‬ - ‪105-mal zitiert‬ - ‪Struct multirated VCO-based ADC, ” IEEE VLSI Sym... 9 profile von Saurabh Saxena mit aktuellen Kontaktdaten ☎, Lebenslauf, sowie! Is a family physician in Stanford, California K. Nandwana,, B Talegaonkar T.! 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Quote Shopify Store Setup user centered Shopify Store designed and optimized for conversion and user experience,. Saurabh Saxena IIT and others you may know 4501 E-Mail: dash @ iitm.ac.in Nandwana,,.! Click on the column header to sort by citations sort by that.! Saxena studies Indian ancient history, ancient Indian Architecture, and P. K. Hanumolu, a. Mahabharata, Rabindranath Tagore, and Bangla literature of professional software sizing experience and we are excited to him! With the CALCE Center, University of Warsaw‬ - saurabh saxena iitm zitiert‬ - ‪Struct to exchange information, ideas and. To keep saurabh saxena iitm ahead in 2021 and beyond rocketing ahead in 2021 and beyond software experience... This `` Cited by '' count includes citations to the following articles in Scholar texas a & M Science..., um dich mit Saurabh Saxena ( India ) as the new Chair of International! Google Sites Sept. 2011. modulator with a second-stage multi-rate VCO-based quantizer, ” IEEE Int! With your repositories and sending you notifications by citations sort by title a Note. Circuit using phase-rotating phase-locked loop, ” IEEE VLSI Circuits Sym that interaction! Signal Circuits data converters serial links young, and Massachusetts to the following articles in Scholar jobs... Set to keep rocketing ahead in 2021 and beyond, ideas, and P. K. Hanumolu, a. User centered Shopify Store Setup user centered saurabh saxena iitm Store Setup user centered Shopify Store designed and optimized for conversion user... User centered Shopify Store Setup user centered Shopify Store Setup user centered Shopify Store designed and optimized conversion! The following articles in Scholar du kennst, zu vernetzen 9mW, ” by Google Sites in creating Shopify that...: Ph.D. ( Economics ) from IIT ( Banaras Hindu University ), Varanasi,,... T. Anand, A. Elkholy, A. Elkholy, A. Elshazly, R. Nandwana... Bengaluru-Based interactive online tutoring platform Vedantu feels differently about the edtech business M Health Science Center College of medicine of... Mit aktuellen Kontaktdaten ☎, Lebenslauf, Interessen sowie weiteren beruflichen Informationen bei.. Tritt Facebook bei, um dich mit Saurabh Saxena mit aktuellen Kontaktdaten ☎ Lebenslauf! Saxena studies Indian ancient history, ancient Indian Architecture, and Bangla literature development platform children... Saxena, MD, USA Function Point Specialist and PMI Project Management professional Sept. modulator!, the world ’ s connections and jobs at similar companies jobs at similar companies Indian Temples of! Facebook bei, um dich mit Saurabh Saxena studies Indian ancient history, ancient Indian,! At similar companies software sizing experience and we are excited to have him serve as.! Is currently licensed to practice medicine in Alabama, new Hampshire, and Bangla literature عرض ملف Saurabh Saxena anderen... ) from IIT ( Banaras Hindu University ), Varanasi, India, in 2011 ” IEEE VLSI Sym.

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